Flip chip technology plays an important role in the packaging of semiconductor devices. A flip chip microelectronic assembly includes a direct electrical connection of face down electronic components onto substrates, such as circuit boards, using solder bumps as the interconnects. The use of flip chip packaging has dramatically grown as a result of the advantages in size, performance, and flexibility flip chips have over other packaging methods.
Recently, copper pillar technology has been developed. Instead of using solder bumps, electronic components are connected to substrates by means of a copper pillar. Copper pillar technology achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load of the circuits, and allows the electronic components to perform at higher frequencies.
However, conventional solder bump and copper pillar manufacturing processes have shortcomings. For example, during the formation of a conventional solder bump, the solder is used as a mask to etch the underlying the under bump metallurgy (UBM) layer. However, the UBM layer may be attacked laterally in the etching process that results in an undercut of the UBM layer. The undercut of the UBM layer may induce stress during the solder bump manufacturing process. The stress may cause cracks in the underlying low dielectric constant (low-K) dielectric layers of the substrate. In copper pillar manufacturing processes, stress may cause cracks along the interface of the copper pillar and the solder used to bond the electronic component. The stress may also lead to cracks along the interface of the underfill and the copper pillar. The cracks may cause serious reliability concerns due to high leakage currents.
Accordingly, there is a need for an improved structure and method to form conductive pillar for a semiconductor wafer with robust electrical performance.